DeBruin Scale
Idea · WIP

Semiconductor hardware grading

The DeBruin Scale — Every Chip Gets a Grade.

A proposed independent grading language for semiconductor hardware — analogous to diamond grading: measure the hard parts, then give buyers a simple overall grade.

Research / standards idea. Not a live certification authority. Not a fab yield product. Not affiliated with any chip vendor. Thresholds TBD pending real hardware stats.

The problem

Manufacturers already test and bin chips. The same model number can still hide very different histories — nearly new vs years under heavy thermal load. Buyers lack a manufacturer-independent way to compare usable capability and condition.

Four certification levels

Die

Individual die: functional units, clocks, leakage, thermal, I/O, stability.

Package

Packaged / chiplet devices: interconnect, integrity, interfaces.

Accelerator

Complete AI accelerators — where memory and interconnect matter most.

System

Servers, appliances, rack-scale — plus power, cooling, multi-device reliability.

Four dimensions (0–100)

Compute

Usable capability vs expected spec under sustained load.

Capacity

Memory and related capacity, errors, bandwidth.

Connectivity

PCIe, NVLink/equivalent, chiplet and high-speed I/O health.

Condition

Stability, thermal/power behavior, age, degradation — critical for used gear.

Overall grade (AAA→F)

Conceptual meanings only — numeric cutoffs wait on statistically defensible testing.

GradeMeaning
AAAExceptional / essentially full-spec
AAExcellent
AHigh quality
BReliable compute-grade with measurable limits
CValue compute; selected workloads
DSalvage-grade; specialized applications
FNot suitable for certified compute use

Where it starts

Immediate focus is the secondary AI hardware market — finished accelerators first — not fab scrap. Model number alone does not answer residual value.

Business model (Idea·WIP): certification · labs · marketplace · API · fleet assessment. No “buy a certificate” CTA yet — the standard comes first.